1. Field of the Invention
The present invention relates to lock detectors for phase-locked loops (PLL), and particularly to an adjustable digital lock detector.
2. Description of the Prior Art
Phase-locked loops (PLL) are a category of electronic circuits that generate an oscillating signal having phase and frequency matching an incoming signal. In practical application, the PLL can be used for generating a clock signal (the oscillating signal) that tracks the phase and frequency of a data signal (the incoming signal). In addition to synchronization applications, as described above, the PLL can also be used to demodulate frequency modulated (FM) signals, and as frequency synthesizers for generating stable, high-frequency clock signals from a lower frequency reference signal.
It is of interest to other circuits that utilize the clock signal generated by the PLL to know when the clock signal is locked to the data signal. In general, a lock detector is a circuit utilized to provide a lock indicator when the clock signal and the data signal are synchronized. In practice, a perfect phase/frequency lock between the clock signal and the data signal is impossible, and typically an acceptable amount of error is present in the phase/frequency lock. Thus, the lock detector will often determine whether the errors in the phases/frequencies of the clock signal and the data signal are within a specific window.
Please refer to FIG. 1, which is a diagram of a lock detector 100 according to the prior art. The lock detector 100 compares a reference clock CLKREF to an oscillator clock CLKVCO to generate a lock signal LOCK. The lock detector 100 comprises a frequency divider 102, an edge detector 104, a counter 106, a detector 108, a first delay circuit 110, a second delay circuit 112, and a phase sampler 114. The frequency divider 102 receives the reference clock CLKREF, and divides it by N. The edge detector 104 detects positive or negative edges of the divided oscillator clock such that the counter 106 counts edges of the divided oscillator clock to generate a count number M. When the count number M is equal to N, the frequencies of the reference clock CLKREF and the oscillator clock CLKVCO are matched. The phase sampler 114 compares the reference clock CLKREF after the first delay circuit 110 with the oscillator clock CLKVCO. If the phase of the delayed reference clock falls between the phase of the oscillator clock CLKVCO and the phase of the oscillator clock CLKVCO after the second delay circuit 112, i.e. a locking window, the phase sampler 114 generates the lock signal LOCK, indicating that the PLL has successfully locked the frequency and the phase.
In the lock detector 100 of the prior art, the first delay circuit 110 and the second delay circuit 112 are both analog delay circuits. Thus, the delays provided by the first delay circuit 110 and the second delay circuit 112 are susceptible to process, temperature, and bias voltage variation.